1. Field of the Invention
The present invention relates to a technology for executing a process redundantly by a plurality of CPUs.
2. Description of the Related Art
Thanks to the recent proliferation of an information technology (IT) into our society, a variety of information systems utilizing the IT is provided to our society. Information/communication equipment for realizing these systems is becoming a necessary and indispensable lifeline of social infrastructure in our modern society and an enormous amount of information processing must always be executed without stoppage. In order to meet such a requirement, information/communication equipment constituting an information system must process an enormous amount of information rapidly and without delay. Therefore, in order to meet such a requirement, in a system for processing a large amount of information rapidly and securely, such as a communication system or the like, devices in which a plurality of CPUs is provided and a hardware configuration for executing load distribution control is adopted are used.
FIG. 1 shows a conventional processing circuit. The processing circuit 100 comprises a plurality of CPUs 101 (Nos. 0 through m in FIG. 1), common memory 102 for performing a synchronous process among the CPUs, a plurality of I/O units 103 (Nos. 0 through n in FIG. 1) for externally inputting/outputting data, which are connected to each other by a common bus. The processing circuit with the configuration shown in FIG. 1 adopts a method in which an interrupt request from the I/O unit 103 is inputted to the plurality of CPUs 101 in parallel in order to distribute load and a CPU 101 that first fetches the interrupt request executes it, or a method for transferring a transaction to each CPU 101 and executing it. Also, for the hardware configuration for exercising load distribution control, a full running configuration in which all processing circuits are used as running or an N+1 configuration being a redundant configuration is used.
Also, a multiple computer system is provided with a technology for modifying a redundancy system according to the number of CPUs or the degree of importance of data (for example, Patent reference 1).
Patent reference 1: Japanese Patent Application Publication No. S60-55464
In the conventional processing circuit, a plurality of CPUs is connected in parallel by a common bus, when the common bus interface hardware fails, the system cannot operate. When load increases and the frequency of the access to the common bus of a CPU increases, the functionality is hindered due to the bottle-neck of the bus. Furthermore, when a CPU fails, there is no way to relieve a transaction being processed in the failed CPU.